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CY7C4255, CY7C4265, CY7C4265A
8K/16K x 18 Deep Sync FIFOs
Features
Functional Description
The CY7C4255/65/65A are high speed, low power, first-in first-out (FIFO) memories with clocked read and write interfaces. All are 18 bits wide and are pin/functionally compatible to the CY7C42X5 Synchronous FIFO family. The CY7C4255/65/65A can be cascaded to increase FIFO depth. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high speed data acquisition, multiprocessor interfaces, and communications buffering. These FIFOs have 18-bit input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a free running Clock (WCLK) and a Write Enable pin (WEN). When WEN is asserted, data is written into the FIFO on the rising edge of the WCLK signal. While WEN is held active, data is continually written into the FIFO on each cycle. The output port is controlled in a similar manner by a free-running Read Clock (RCLK) and a Read Enable pin (REN). In addition, the CY7C4255/65/65A have an Output Enable pin (OE). The read and write clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. Clock frequencies up to 100 MHz are achievable. Retransmit and Synchronous Almost Full/Almost Empty flag features are available on these devices. Depth expansion is possible using the Cascade Input (WXI, RXI), Cascade Output (WXO, RXO), and First Load (FL) pins. The WXO and RXO pins are connected to the WXI and RXI pins of the next device, and the WXO and RXO pins of the last device should be connected to the WXI and RXI pins of the first device. The FL pin of the first device is tied to VSS and the FL pin of all the remaining devices should be tied to VCC.
D0-17 INPUT REGISTER
High Speed, Low Power, First-In First-Out (FIFO) Memories 8K x 18 (CY7C4255) [1] 16K x 18 (CY7C4265/4265A) 0.5 Micron CMOS for Optimum Speed and Power High Speed 100 MHz Operation (10 ns read/write cycle times) Low Power -- ICC = 45 mA Fully Asynchronous and Simultaneous Read and Write Operation Empty, Full, Half Full, and Programmable Almost Empty and Almost Full Status Flags TTL compatible Retransmit Function Output Enable (OE) Pins Independent Read and Write Enable Pins Center Power and Ground Pins for Reduced Noise Supports Free-running 50 percent Duty Cycle Clock Inputs Width and Depth Expansion Capability 64-pin TQFP and 64-pin STQFP Pin-compatible Density Upgrade to CY7C42X5 Family Pin-compatible Density Upgrade to IDT72205/15/25/35/45 Pb-free Packages Available

Logic Block Diagram
WCLK
WEN
WRITE CONTROL
FLAG PROGRAM REGISTER
RAM ARRAY 8K x 18 16K x 18 WRITE POINTER
FLAG LOGIC
FF EF PAE PAF SMODE
READ POINTER
RS
RESET LOGIC
FL/RT WXI WXO/HF RXI RXO
EXPANSION LOGIC
THREE-STATE OUTPUT REGISTER Q0-17 OE
READ CONTROL RCLK
REN
Note 1. CY7C4265 and CY7C4265A are functionally identical
Cypress Semiconductor Corporation Document #: 38-06004 Rev. *E
*
198 Champion Court
*
San Jose, CA 95134-1709
* 408-943-2600 Revised June 03, 2009
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CY7C4255, CY7C4265, CY7C4265A
Pin Configurations
Figure 1. 64-Pin TQFP/STQFP (Top View)
REN LD OE RS VCC GND EF Q17 Q16 GND Q15 VCC/SMODE D16 D17 GND RCLK
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
FL/RT WCLK WEN WXI VCC PAF RXI FF WXO/HF RXO
PAE
Q0 Q1 GND Q2
Pin Description
The CY7C4255/65/65A provides five status pins. These pins are decoded to determine one of five states: Empty, Almost Empty, Half Full, Almost Full, and Full. The Half Full flag shares the WXO pin. This flag is valid in the standalone and width-expansion configurations. In the depth expansion, this pin provides the expansion out (WXO) information that is used to signal the next FIFO when it is activated. The Empty and Full flags are synchronous, that is, they change state relative to either the Read Clock (RCLK) or the Write Clock Table 1. Selection Guide Description Maximum Frequency (MHz) Maximum Access Time (ns) Minimum Cycle Time (ns) Minimum Data or Enable Set-Up (ns) Minimum Data or Enable Hold (ns) Maximum Flag Delay (ns) Active Power Supply Commercial Current (ICC1) (mA) Industrial Table 2. Density and Package Description Density Package CY7C4255 8K x 18 64-pin TQFP, STQFP CY7C4265/65A 16K x18 64-pin TQFP, STQFP 7C4255/65-10 100 8 10 3 0.5 8 45 50 7C4255/65/65A-15 66.7 10 15 4 1 10 45 50 7C4255/65-25 40 15 25 6 1 15 45 50 7C4255/65-35 28.6 20 35 7 2 20 45 50 (WCLK). When entering or exiting the Empty states, the flag is updated exclusively by the RCLK. The flag denoting Full states is updated exclusively by WCLK. The synchronous flag architecture guarantees that the flags remain valid from one clock cycle to the next. The Almost Empty/Almost Full flags become synchronous if the VCC/SMODE is tied to VSS. All configurations are fabricated using an advanced 0.5 CMOS technology. Input ESD protection is greater than 2001V, and latch up is prevented by the use of guard rings.
Document #: 38-06004 Rev. *E
Q3
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CY7C4255 CY7C4265/65A
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
Q14 Q13 GND Q12 Q11 VCC Q10 Q9 GND Q8 Q7 Q6 Q5 GND Q4 VCC
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Table 3. Pin Definitions Signal Name D0 -17 Q0-17 WEN REN WCLK RCLK Description Data Inputs Data Outputs Write Enable Read Enable Write Clock Read Clock I/O I O I I I I Data inputs for an 18-bit bus. Data outputs for an 18-bit bus. Enables the WCLK input. Enables the RCLK input. The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not Full. When LD is asserted, WCLK writes data into the programmable flag-offset register. The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is not Empty. When LD is asserted, RCLK reads data out of the programmable flag-offset register. Dual-Mode Pin: Single device or width expansion - Half Full status flag. Cascaded - Write Expansion Out signal, connected to WXI of next device. When EF is LOW, the FIFO is empty. EF is synchronized to RCLK. When FF is LOW, the FIFO is full. FF is synchronized to WCLK. When PAE is LOW, the FIFO is almost empty based on the almost-empty offset value programmed into the FIFO. PAE is asynchronous when VCC/SMODE is tied to VCC; it is synchronized to RCLK when VCC/SMODE is tied to VSS. When PAF is LOW, the FIFO is almost full based on the almost full offset value programmed into the FIFO. PAF is asynchronous when VCC/SMODE is tied to VCC; it is synchronized to WCLK when VCC/SMODE is tied to VSS. When LD is LOW, D0-17 (Q0-17) are written (read) into (from) the programmable-flag-offset register. Dual-Mode Pin: Cascaded - The first device in the daisy chain has FL tied to VSS; all other devices has FL tied to VCC. In standard mode or width expansion, FL is tied to VSS on all devices. Not Cascaded - Tied to VSS. Retransmit function is also available in stand-alone mode by strobing RT. Cascaded - Connected to WXO of previous device. Not Cascaded - Tied to VSS. Cascaded - Connected to RXO of previous device. Not Cascaded - Tied to VSS. Cascaded - Connected to RXI of next device. Resets device to empty condition. A reset is required before an initial read or write operation after power up. When OE is LOW, the FIFO's data outputs drive the bus to which they are connected. If OE is HIGH, the FIFO's outputs are in High Z (high-impedance) state. Dual-Mode Pin: Asynchronous Almost Empty/Almost Full flags - tied to VCC. Synchronous Almost Empty/Almost Full flags - tied to VSS. (Almost Empty synchronized to RCLK, Almost Full synchronized to WCLK.) Function
WXO/HF
Write Expansion Out/Half Full Flag Empty Flag Full Flag Programmable Almost Empty Programmable Almost Full Load First Load/ Retransmit
O
EF FF PAE
O O O
PAF
O
LD FL/RT
I I
WXI RXI RXO RS OE VCC/SMODE
Write Expansion Input Read Expansion Input Read Expansion Output Reset Output Enable Synchronous Almost Empty/ Almost Full Flags
I I O I I I
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Maximum Ratings
Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested.[2] Storage Temperature ................................ -65C to +150C Ambient Temperature with Power Applied. -55C to +125C Supply Voltage to Ground Potential................-0.5V to +7.0V DC Voltage Applied to Outputs in High Z State ................................................-0.5V to +7.0V DC Input Voltage ......................................... -0.5V to VCC+0.5V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage............................................ >2001V (per MIL-STD-883, Method 3015) Latch Up Current ..................................................... >200 mA
Operating Range
Range Commercial Industrial[4] Ambient Temperature[3] 0C to +70C -40C to +85C VCC 5V 10% 5V 10%
Electrical Characteristics Over the Operating Range[4]
Parameter VOH VOL VIH[5] VIL[5] IIX IOZL IOZH ICC1[6] ICC2
[7]
Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output OFF, High Z Current Active Power Supply Current Average Standby Current
Test Conditions VCC = Min., IOH = -2.0 mA VCC = Min., IOL = 8.0 mA
7C42X5-10
7C42X5, 7C4265A-15
7C42X5-25
7C42X5-35
Unit V
Min 2.4
Max
Min 2.4
Max
Min 2.4
Max
Min 2.4
Max
0.4 2.0 -0.5 VCC 0.8 +10 +10 45 50 10 15 2.0 -0.5 -10 -10
0.4 VCC 0.8 +10 +10 45 50 10 15 2.0 -0.5 -10 -10
0.4 VCC 0.8 +10 +10 45 50 10 15 2.0 -0.5 -10 -10
0.4 VCC 0.8 +10 +10 45 50 10 15
V V V A A mA mA mA mA
VCC = Max. OE > VIH, VSS < VO < VCC Commercial Industrial Commercial Industrial
-10 -10
Capacitance[8, 9]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max 5 7 Unit pF pF
Notes 2. The Voltage on any input or I/O pin cannot exceed the power pin during power up. 3. TA is the "Instant On" case temperature. 4. See the last page of this specification for Group A subgroup testing information. 5. The VIH and VIL specifications apply for all inputs except WXI, RXI. The WXI, RXI pin is not a TTL input. It is connected to either RXO, WXO of the previous device or VSS. 6. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at 20 MHz, while data inputs switch at 10 MHz. Outputs are unloaded. ICC1(typical) = (25 mA + (freq - 20 MHz) * (1.0 mA/MHz)). 7. All inputs = VCC - 0.2V, except RCLK and WCLK (which are switching at frequency = 20 MHz), and FL/RT which is at VSS. All outputs are unloaded. 8. Tested initially and after any design changes that may affect these parameters. 9. Tested initially and after any process changes that may affect these parameters.
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Figure 2. AC Test Loads and Waveforms[10, 11]
R1 1.1 K 5V OUTPUT CL INCLUDING JIG AND SCOPE R2 680 3.0V GND 3 ns
ALL INPUT PULSES
90% 10% 90% 10% 3 ns
Equivalent to:
THEVENIN EQUIVALENT 410 OUTPUT
1.91V
Switching Characteristics Over the Operating Range
Parameter tS tA tCLK tCLKH tCLKL tDS tDH tENS tENH tRS tRSR tRSF tPRT tRTR tOLZ tOE tOHZ tWFF tREF tPAFasynch tPAFsynch tPAEasynch tPAEsynch tHF tXO Description Clock Cycle Frequency Data Access Time Clock Cycle Time Clock HIGH Time Clock LOW Time Data Set Up Time Data Hold Time Enable Set Up Time Enable Hold Time Reset Pulse Width[12] Reset Recovery Time Reset to Flag and Output Time Retransmit Pulse Width Retransmit Recovery Time Output Enable to Output in Low Z Output Enable to Output Valid Output Enable to Output in High Z[13] Write Clock to Full Flag Read Clock to Empty Flag Clock to Programmable Almost-Full Flag[13] (Asynchronous mode, VCC/SMODE tied to VCC) Clock to Programmable Almost-Full Flag (Synchronous mode, VCC/SMODE tied to VSS) Clock to Programmable Almost-Empty Flag[14] (Asynchronous mode, VCC/SMODE tied to VCC) Clock to Programmable Almost-Full Flag (Synchronous mode, VCC/SMODE tied to VSS) Clock to Half-Full Flag Clock to Expansion Out
[12]
7C42X5-10
7C42X5, 7C4265A-15
7C42X5-25
7C42X5-35
Unit
Min 2 10 4.5 4.5 3 0.5 3 0.5 10 8
Max 100 8
Min 2 15 6 6 4 1 4 1 15 10
Max 66.7 10
Min 2 25 10 10 6 1 6 1 25 15
Max 40 15
Min 2 35 14 14 7 2 7 2 35 20
Max 28.6 20 MHz ns ns ns ns ns ns ns ns ns ns 35 ns ns ns ns 15 15 20 20 25 20 25 20 25 20 ns ns ns ns ns ns ns ns ns ns Page 5 of 23
10 30 60 0 3 3 7 7 8 8 12 8 12 8 12 6 35 65 0 3 3
15 45 75 0 8 8 10 10 16 10 16 10 16 10 3 3
25 55 85 0 12 12 15 15 20 15 20 15 20 15 3 3
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Switching Characteristics Over the Operating Range (continued)
Parameter tXI tXIS tSKEW1 tSKEW2 tSKEW3 Description Expansion in Pulse Width Expansion in Set-Up Time Skew Time between Read Clock and Write Clock for Full Flag Skew Time between Read Clock and Write Clock for Empty Flag Skew Time between Read Clock and Write Clock for Programmable Almost Empty and Programmable Almost Full Flags (Synchronous Mode only)
7C42X5-10 7C42X5, 7C4265A-15 7C42X5-25 7C42X5-35
Unit
Min 4.5 4 5 5 10
Max
Min 6.5 5 6 6 15
Max
Min 10 10 10 10 18
Max
Min 14 15 12 12 20
Max ns ns ns ns ns
Notes 10. CL = 30 pF for all AC parameters except for tOHZ. 11. CL = 5 pF for tOHZ. 12. Pulse widths less than minimum values are not enabled. 13. Values guaranteed by design, not currently tested. 14. tPAFasynch, tPAEasynch, after program register write is not be valid until 5 ns + tPAF(E).
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Switching Waveforms
Figure 3. Write Cycle Timing
tCLK
tCLKH WCLK
tCLKL
tDS D0 -D17 tENS WEN tWFF FF tSKEW1 [15] RCLK
tDH
tENH
NO OPERATION
tWFF
REN
Figure 4. Read Cycle Timing
tCLK
tCLKH RCLK tENS REN tREF EF tA Q0 -Q17 tOLZ OE tOE tENH
tCLKL
NO OPERATION
tREF
VALID DATA
tOHZ
[16] tSKEW2
WCLK
WEN
Notes 15. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF goes HIGH during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK rising edge. 16. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF goes HIGH during the current clock cycle. It the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then EF may not change state until the next RCLK rising edge.
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Switching Waveforms (continued)
Figure 5. Reset Timing[17]
tRS tRSR REN, WEN, LD tRSF EF,PAE tRSF FF,PAF, HF tRSF Q0-Q17 OE = 1 OE = 0
[18]
RS
Figure 6. First Data Word Latency after Reset with Simultaneous Read and Write
WCLK tDS D0 -D17 tENS WEN tSKEW2 RCLK tREF EF D0 (FIRSTVALID WRITE)
[19]
D1
D2
D3
D4
tFRL
REN tA Q0 -Q17 tOLZ OE tOE tA D0
[20]
D1
Notes 17. The clocks (RCLK, WCLK) can be free-running during reset. 18. After reset, the outputs are LOW if OE = 0 and three-state if OE = 1. 19. When tSKEW2 > minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW2 or tCLK + tSKEW2. The Latency Timing applies only at the Empty Boundary (EF = LOW). 20. The first word is available the cycle after EF goes HIGH, always.
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Switching Waveforms (continued)
Figure 7. Empty Flag Timing
WCLK tDS D0 -D17 tENS WEN tFRL RCLK tSKEW2 EF REN OE tA Q0 -Q17 D0 tREF tREF tSKEW2 tREF
[19]
tDS D0 tENH tENS D1 tENH tFRL[19]
Figure 8. Full Flag Timing
NO WRITE WCLK tSKEW1 D0 -D17 tWFF FF
[15]
NO WRITE
tDS
tSKEW1 [15] DATA WRITE tWFF tWFF
DATA WRITE
WEN
RCLK tENS REN tENH tENS tENH
OE
LOW tA tA DATA READ NEXT DATA READ
Q0 -Q17
DATA IN OUTPUT REGISTER
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Switching Waveforms (continued)
Figure 9. Half-Full Flag Timing
tCLKH WCLK tENS tENH WEN tHF HF HALF FULL OR LESS HALF FULL + 1 OR MORE tHF RCLK tENS REN tCLKL
HALF FULLOR LESS
Figure 10. Programmable Almost Empty Flag Timing
tCLKH WCLK tENS tENH WEN tPAE PAE [21] N + 1 WORDS IN FIFO tPAE n WORDS IN FIFO tCLKL
RCLK tENS REN
Note 21. PAE is offset = n. Number of data words into FIFO already = n.
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Switching Waveforms (continued)
Figure 11. Programmable Almost Empty Flag Timing (applies only in SMODE (SMODE is LOW))
tCLKH WCLK tENS tENH WEN tCLKL
WEN2 tENS tENH PAE tSKEW3 RCLK tENS REN tENS tENH
[23]
Note 22 tPAE synch
N + 1 WORDS INFIFO
Note 24
tPAE synch
Figure 12. Programmable Almost Full Flag Timing
tCLKH WCLK Note 25 tENS tENH WEN tPAF PAF
[26]
tCLKL
FULL- M WORDS [27] INFIFO tPAF
FULL- (M+1) WORDS [28] IN FIFO
RCLK tENS REN
Notes 22. PAE offset - n. 23. tSKEW3 is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK and the rising RCLK is less than tSKEW3, then PAE may not change state until the next RCLK. 24. If a read is preformed on this rising edge of the read clock, there are Empty + (n-1) words in the FIFO when PAE goes LOW. 25. PAF offset = m. Number of data words written into FIFO already = 8192 - (m + 1) for the CY7C4255 and 16384 - (m + 1) for the CY7C4265/65A. 26. PAF is offset = m. 27. 8192 - m words in CY7C4255 and 16384 - m words in CY7C4265/65A. 28. 8192 - (m + 1) words in CY7C4255 and 16384 - (m + 1) CY7C4265/65A.
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Switching Waveforms (continued)
Figure 13. Programmable Almost Full Flag Timing (applies only in SMODE (SMODE is LOW))
tCLKH WCLK tENS tENH WEN Note WEN2 tENS tENH PAF FULL- M + 1 WORDS IN FIFO
30
tCLKL
Note 29
tPAF FULL- M [27] WORDS IN FIFO tSKEW3[31] tPAF synch
RCLK tENS REN tENS tENH
Figure 14. Write Programmable Registers
tCLK tCLKH WCLK tENS LD tENS WEN tDS D0 -D17 PAE OFFSET PAF OFFSET D0 - D11 tDH PAE OFFSET tENH tCLKL
Notes 29. If a write is performed on this rising edge of the write clock, there are Full - (m - 1) words of the FIFO when PAF goes LOW. 30. PAF offset = m. 31. tSKEW3 is the minimum time between a rising RCLK and a rising WCLK edge for PAF to change state during that clock cycle. If the time between the edge of RCLK and the rising edge of WCLK is less than tSKEW3, then PAF may not change state until the next WCLK rising edge.
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Switching Waveforms (continued)
Figure 15. Read Programmable Registers
tCLK tCLKH RCLK tENS LD tENS WEN tA Q0 -Q17 UNKNOWN PAE OFFSET PAF OFFSET PAE OFFSET tENH tCLKL
Figure 16. Write Expansion Out Timing
tCLKH WCLK
Note 32
tXO
WXO tENS WEN
Note 32
tXO
Figure 17. Read Expansion Out Timing
tCLKH WCLK Note 33 tXO RXO tENS REN tXO
Figure 18. Write Expansion In Timing
tXI WXI
WCLK
Notes 32. Write to Last Physical Location. 33. Read from Last Physical Location.
tXIS
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Switching Waveforms (continued)
Figure 19. Read Expansion In Timing
tXI RXI tXIS
RCLK
Figure 20. Retransmit Timing[34, 35, 36]
FL/RT tPRT tRTR REN/WEN
EF/FF and all async flags HF/PAE/PAF
Notes 34. Clocks are free-running in this case. 35. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags are valid at tRTR. 36. For the synchronous PAE and PAF flags (SMODE), an appropriate clock cycle is necessary after tRTR to update these flags.
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Architecture
The CY7C4256/65 consists of an array of 8K/16K words of 18 bits each (implemented by a dual-port array of SRAM cells), a read pointer, a write pointer, control signals (RCLK, WCLK, REN, WEN, RS), and flags (EF, PAE, HF, PAF, FF). The CY7C4255/65/65A also includes the control signals WXI, RXI, WXO, RXO for depth expansion.
read/write operation. When the LD pin is set LOW, and WEN is LOW, the next offset register in sequence is written. The contents of the offset registers can be read on the output lines when the LD pin is set LOW and REN is set LOW; then, data can be read on the LOW-to-HIGH transition of the Read Clock (RCLK). Table 4. Write Offset Register LD 0 WEN 0 WCLK[37] Selection Writing to offset registers: Empty Offset Full Offset No Operation Write Into FIFO No Operation
Resetting the FIFO
Upon power up, the FIFO must be reset with a Reset (RS) cycle. This causes the FIFO to enter the Empty condition signified by EF being LOW. All data outputs go LOW after the falling edge of RS only if OE is asserted. For the FIFO to reset to its default state, a falling edge must occur on RS and the user must not read or write while RS is LOW.
0 1 1
1 0 1
FIFO Operation
When the WEN signal is active (LOW), data present on the D0-17 pins is written into the FIFO on each rising edge of the WCLK signal. Similarly, when the REN signal is active LOW, data in the FIFO memory are presented on the Q0-17 outputs. New data is presented on each rising edge of RCLK while REN is active LOW and OE is LOW. REN must set up tENS before RCLK for it to be a valid read function. WEN must occur tENS before WCLK for it to be a valid write function. An output enable (OE) pin is provided to three-state the Q0-17 outputs when OE is deasserted. When OE is enabled (LOW), data in the output register is available to the Q0-17 outputs after tOE. If devices are cascaded, the OE function only outputs data on the FIFO that is read enabled. The FIFO contains overflow circuitry to disallow additional writes when the FIFO is full, and under flow circuitry to disallow additional reads when the FIFO is empty. An empty FIFO maintains the data of the last valid read on its Q0-17 outputs even after additional reads occur.
Flag Operation
The CY7C4255/65/65A devices provide five flag pins to indicate the condition of the FIFO contents. Empty and Full are synchronous. PAE and PAF are synchronous if VCC/SMODE is tied to VSS.
Full Flag
The Full Flag (FF) goes LOW when device is Full. Write operations are inhibited whenever FF is LOW regardless of the state of WEN. FF is synchronized to WCLK: it is exclusively updated by each rising edge of WCLK.
Empty Flag
The Empty Flag (EF) goes LOW when the device is empty. Read operations are inhibited whenever EF is LOW, regardless of the state of REN. EF is synchronized to RCLK, i.e., it is exclusively updated by each rising edge of RCLK.
Programming
The CY7C4255/65/65A devices contain two 14-bit offset registers. Data present on D0-13 during a program write determines the distance from Empty (Full) that the Almost Empty (Almost Full) flags become active. If the user elects not to program the FIFO's flags, the default offset values are used (see Table 4). When the Load LD pin is set LOW and WEN is set LOW, data on the inputs D0-13 is written into the Empty offset register on the first LOW-to-HIGH transition of the Write Clock (WCLK). When the LD pin and WEN are held LOW then data is written into the Full offset register on the second LOW-to-HIGH transition of the Write Clock (WCLK). The third transition of the Write Clock (WCLK) again writes to the Empty offset register (see Table 4). Writing all offset registers does not have to occur at one time. One or two offset registers can be written and then, by bringing the LD pin HIGH, the FIFO is returned to normal
Programmable Almost Empty/Almost Full Flag
The CY7C4255/65/65A features programmable Almost Empty and Almost Full Flags. Each flag can be programmed (described in the Programming section) a specific distance from the corresponding boundary flags (Empty or Full). When the FIFO contains the number of words or fewer for which the flags have been programmed, the PAF or PAE are asserted, signifying that the FIFO is either Almost Full or Almost Empty. See Table 5 on page 16 for a description of programmable flags. When the SMODE pin is tied LOW, the PAF flag signal transition is caused by the rising edge of the write clock and the PAE flag transition is caused by the rising edge of the read clock.
Note 37. The same selection sequence applies to reading from the registers. REN is enabled and read is performed on the LOW-to-HIGH transition of RCLK.
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CY7C4255, CY7C4265, CY7C4265A
Retransmit
The retransmit feature is beneficial when transferring packets of data. It enables the receipt of data to be acknowledged by the receiver and retransmitted if necessary. The Retransmit (RT) input is active in the stand-alone and width expansion modes. The retransmit feature is intended for use when a number of writes equal to or less than the depth of the FIFO have occurred and at least one word has been read since the last RS cycle. A HIGH pulse on RT resets the internal read Table 5. Flag Truth Table Number of Words in FIFO CY7C4255 - 8K x 18 0 1 to n[38] (n + 1) to 4096 4097 to (8192 - (m + 1)) (8192 - 8192 m)[39] to 8191 0 1 to n[38] (n + 1) to 8192 8193 to (16384 - (m + 1)) (16384 - 16384 m)[39] to 16383 CY7C4265/65A - 16K x 18
pointer to the first physical location of the FIFO. WCLK and RCLK may be free running but must be disabled during and tRTR after the retransmit pulse. With every valid read cycle after retransmit, previously accessed data is read and the read pointer is incremented until it is equal to the write pointer. Flags are governed by the relative locations of the read and write pointers and are updated during a retransmit cycle. Data written to the FIFO after activation of RT are transmitted also. The full depth of the FIFO can be repeatedly retransmitted.
FF H H H H H L
PAF H H H H L L
HF H H H L L L
PAE L L H H H H
EF L H H H H H
Notes 38. n = Empty Offset (Default Values: CY7C4255/CY7C4265/65A n = 127). 39. m = Full Offset (Default Values: CY7C4255/CY7C4265/65A n = 127).
Document #: 38-06004 Rev. *E
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CY7C4255, CY7C4265, CY7C4265A
Width Expansion Configuration
The CY7C4255/65/65A can be expanded in width to provide word widths greater than 18 in increments of 18. During width expansion mode all control line inputs are common and all flags are available. Empty (Full) flags should be created by ANDing the Empty (Full) flags of every FIFO; the PAE and PAF flags can be detected from any one device. This technique avoids reading data from, or writing data to the FIFO that is "staggered" by one clock cycle due to the variations in skew between RCLK and WCLK. Figure 21 demonstrates a 36-word width by using two CY7C4255/65/65As. Figure 21. Block Diagram of 8K x18/16K x 18 Synchronous FIFO Memory Used in a Width Expansion Configuration
RESET (RS) DATA IN (D) 36
18 18
RESET (RS) READ CLOCK (RCLK) READ ENABLE (REN) OUTPUT ENABLE (OE)
WRITE CLOCK (WCLK) WRITE ENABLE (WEN) LOAD (LD) PROGRAMMABLE(PAE) HALF FULL FLAG (HF) FF FULL FLAG (FF)
18
7C4255 7C4265 7C4255 7C4265
PROGRAMMABLE (PAF)
EMPTY FLAG (EF) EF FF EF
18
DATA OUT (Q)
36
FIRST LOAD (FL) WRITE EXPANSION IN (WXI) READ EXPANSION IN (RXI)
Depth Expansion Configuration (with Programmable Flags)
The CY7C4255/65/65A can easily be adapted to applications requiring more than 8192/16384 words of buffering. Figure 22 shows Depth Expansion using three CY7C42X5s. Maximum depth is limited only by signal loading. Follow these steps: 1. The first device must be designated by grounding the First Load (FL) control input. 2. All other devices must have FL in the HIGH state. 3. The Write Expansion Out (WXO) pin of each device must be tied to the Write Expansion In (WXI) pin of the next device. 4. The Read Expansion Out (RXO) pin of each device must be tied to the Read Expansion In (RXI) pin of the next device. 5. All Load (LD) pins are tied together. 6. The Half-Full Flag (HF) is not available in the Depth Expansion Configuration. 7. EF, FF, PAE, and PAF are created with composite flags by ORing together these respective flags for monitoring. The composite PAE and PAF flags are not precise.
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Figure 22. Block Diagram of 8Kx18/16Kx18 Synchronous FIFO Memory with Programmable Flags used in Depth Expansion Configuration
WXO RXO 7C4255 7C4265 VCC FL FF EF PAE PAF WXI RXI
WXO RXO 7C4255 7C4265 VCC FL FF EF PAF PAE WXI RXI
DATA IN(D)
DATA OUT (Q)
WRITE CLOCK(WCLK) WRITE ENABLE(WEN) RESET (RS) LOAD (LD) FF PAF FF
WXO RXO 7C4255 7C4265
READ CLOCK(RCLK) READ ENABLE(REN) OUTPUT ENABLE(OE)
EF PAE
EF
PAFWXI RXI PAE FIRST LOAD (FL)
Document #: 38-06004 Rev. *E
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CY7C4255, CY7C4265, CY7C4265A
Figure 23. Typical AC and DC Characteristics
NORMALIZED tA vs. SUPPLY VOLTAGE 1.20 NORMALIZED tA 1.10 1.00 0.90 0.80 4.00 NORMALIZED tA NORMALIZED tA vs. AMBIENT TEMPERATURE 1.60 1.40 1.20 1.00 0.80 0.60 -55.00 VCC = 5.0V
TA = 25C
4.50
5.00
5.50
6.00
5.00
65.00
125.00
SUPPLY VOLTAGE (V) NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.40 NORMALIZED ICC 1.20 1.00 0.80 0.60 4.00 VIN = 3.0V TA = 25C f = 28 MHz 4.50 5.00 5.50 6.00 NORMALIZED ICC
AMBIENT TEMPERATURE (C) NORMALIZED SUPPLY CURRENT vs. FREQUENCY 1.75 NORMALIZED ICC 1.50 1.25 1.00 0.75 0.50 20.00 VCC = 5.0V TA = 25C VIN = 3.0V 30.00 40.00 50.00 60.00
NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE 1.20 1.10 1.00 0.90 0.80 -55.00 VIN = 3.0V VCC = 5.0V f = 28 MHz 5.00 65.00 125.00
SUPPLY VOLTAGE (V)
AMBIENT TEMPERATURE (C)
FREQUENCY (MHz)
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CY7C4255, CY7C4265, CY7C4265A
Ordering Information
8Kx18 Deep Sync FIFO Speed (ns) 10 Ordering Code CY7C4255-10AC CY7C4255-10AXC CY7C4255-10ASC 15 CY7C4255-15AC CY7C4255-15AXC 16Kx18 Deep Sync FIFO Speed (ns) 10 Ordering Code CY7C4265-10AC CY7C4265-10ASC CY7C4265-10ASXC CY7C4265-10AI CY7C4265-10AXI 15 CY7C4265-15AC CY7C4265-15AXC CY7C4265-15ASC CY7C4265A-15ASI Package Diagram 51-85046 51-85051 51-85051 51-85046 51-85046 51-85046 51-85046 51-85051 51-85051 Package Type 64-Pin Thin Quad Flatpack 64-Pin Small Thin Quad Flatpack 64-Pin Small Thin Quad Flatpack (Pb-free) 64-Pin Thin Quad Flatpack 64-Pin Thin Quad Flatpack (Pb-free) 64-Pin Thin Quad Flatpack 64-Pin Thin Quad Flatpack (Pb-free) 64-Pin Small Thin Quad Flatpack 64-Pin Small Thin Quad Flatpack Industrial Commercial Industrial Operating Range Commercial Package Name 51-85046 51-85046 51-85051 51-85046 51-85046 Package Type 64-Pin Thin Quad Flatpack 64-Pin Thin Quad Flatpack (Pb-free) 64-Pin Small Thin Quad Flatpack 64-Pin Thin Quad Flatpack 64-Pin Thin Quad Flatpack (Pb-free) Commercial Operating Range Commercial
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CY7C4255, CY7C4265, CY7C4265A
Package Diagrams
Figure 24. 64-Pin Thin Plastic Quad Flat Pack (10 x 10 x 1.4 mm), 51-85051
51-85051 *A
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CY7C4255, CY7C4265, CY7C4265A
Package Diagrams (continued)
Figure 25. 64-Pin Thin Plastic Quad Flat Pack (14 x 14 x 1.4 mm), 51-85046
51-85046-*B 51-85046-*B
Document #: 38-06004 Rev. *E
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CY7C4255, CY7C4265, CY7C4265A
Document History Page
Document Title: CY7C4255, CY7C4265, CY7C4265A 8K/16K X 18 Deep Sync FIFOs Document Number: 38-06004 REV. ** *A *B *C ECN NO. 106465 122257 252889 385985 Orig. of Change SZV RBI YDT ESH Submission Date 07/11/01 12/26/02 See ECN See ECN Description of Change Change from Spec Number: 38-00468 to 38-06004 Power up requirements added to Maximum Ratings Information Removed PLCC package and pruned parts from Order Information Added Pb-Free logo to top of first page Added CY7C4265-10ASXC, CY7C4265-10AXI, CY7C4265-15AXC, CY7C4255-10AXC, CY7C4255-15AXC to ordering information Added CY7C4265A part Updated Ordering information table Corrected defective Logic Block diagram, Pinouts, and Package diagrams
*D *E
2623658 2714768
VKN/PYRS VKN/AESA
12/17/08 06/04/2009
Sales, Solutions, and Legal Information
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(c) Cypress Semiconductor Corporation, 2005-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-06004 Rev. *E
Revised June 03, 2009
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